The fields of technology include integrated circuit structures and processes for making them.
Processes of making integrated circuit structures have line widths of microscopic dimensions currently measured in nanometers (nm). Process generations having different size line widths from each other are called process nodes. An integrated circuit or “chip” generally has a semiconductor substrate (e.g. silicon, silicon germanium or gallium arsenide or other substance), or instead may have an insulating layer, on which semiconductor devices like transistors and diodes are fabricated. Over the semiconductor devices, alternating layers of insulator and conductor are provided, like a layer cake on a cake pan. The conductor layers are patterned and etched into microscopic conducting lines (sometimes called wires and that may have rectangular cross-sections) that are analogous to, but extremely small compared with, say, ordinary electrical conducting wires having a round cross-section as used for home wiring.
The conducting lines are used to interconnect the semiconductor devices to make integrated circuits of varying complexity that under a microscope look like a grid of streets, except at many levels. The conductor layers often are metal but any electrical conductive substance can be useful. One example is polysilicon (poly) which is made conductive for transistor gates and interconnect to the gates. Metal layers for wires are often provided above the poly interconnect layer and interlayer dielectric ILD separates the various layers. Conductive studs called vias are made or deposited through one or more of the ILD layers to electrically connect the conductor layers. Conductive studs are called contacts when they connect the conducting lines at a lower level through dielectric called PMD to integrated semiconductor devices.
To actually implement a particular desired electronic circuit that has been designed and defined by a netlist of the functional electronic circuits, a form of computer software and system is used, called a layout tool or place-and-route tool or simply a tool. The tool situates and defines the geometric arrangement of the transistors, conducting lines, contacts, vias and their interconnections with the semiconductor devices. Tools have constraints, called design rules, that are consistent with the process capabilities and also provide some simplification or order for mathematical algorithms or procedures adopted in a tool to lay out a given complicated integrated circuit and avoid what would otherwise a stupefying and unnecessarily complicated array of geometric possibilities in three dimensions of height, width and depth for the conducting lines that the tool is to define. Structures, placements or geometries that do not conform with design rules are forbidden, and sometimes called “illegal” in the technological sense used in this art.
Newer technologies at advanced semiconductor wafer fabrication process nodes have strong “context effects” where the performance of a transistor depends significantly on what other base layer objects occur near the transistors. Among such base layer objects can be a well beneath transistors (e.g., NWELL), active circuit structures named ACTIVE, Dual Stress Liner (DSL) boundaries of liner over transistors, and length of diffusion LOD from transistor to isolation. Use of standard cells (circuit layout objects) may be difficult in such a technology because each placement of any given cell may have performance that varies with placement and is complicated to estimate because of these context effects.
Context effects have previously generally been “margined for” by accepting an overall degradation in the performance of all of the standard cells. Or they have simply been ignored, detrimentally.
Accordingly, significant departures and alternatives in structures, circuits, processes of manufacture, and processes of design, for addressing the above considerations and problems would be most desirable.